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--- openocd:using_openocd [2021/01/14 17:05] – created ursgraf
+++ openocd:using_openocd [2022/09/16 10:32] (current) – [Problems] ursgraf
@@ Line 1: / Line 1: @@
 ====== Details of Using OpenOCD ======
 OpenOCD starts with a board configuration file. Therein, a configuration file for the processor, the debug interface and a file with initialization sripts can be found.
+===== Scan Chain =====
+Our scan chain contains the PL (programmable logic) and the PS (processing system).
+<code>
+Open On-Chip Debugger 0.10.0
+Licensed under GNU GPL v2
+For bug reports, read
+        http://openocd.org/doc/doxygen/bugs.html
+srst_only separate srst_gates_jtag srst_push_pull connect_deassert_srst
+adapter_nsrst_delay: 40
+Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
+adapter speed: 1000 kHz
+adapter speed: 10000 kHz
+Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
+Info : clock speed 10000 kHz
+Info : JTAG tap: zynq_pl.bs tap/device found: 0x13722093 (mfg: 0x049 (Xilinx), part: 0x3722, ver: 0x1)
+Info : JTAG tap: zynq.dap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)
+Info : zynq.cpu0: hardware has 6 breakpoints, 4 watchpoints
+Info : zynq.cpu1: hardware has 6 breakpoints, 4 watchpoints
+   TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
+-- ------------------- -------- ---------- ---------- ----- ----- ------
+zynq_pl.bs             Y     0x13722093 0x23727093     6 0x01  0x03
+x13722093
+x03727093
+zynq.dap               Y     0x4ba00477 0x4ba00477     4 0x01  0x0f
+</code>
+===== Using Telnet Terminal =====
+Usually, deep will open a telnet connection to the OpenOCD server running on the host (through the OpenOCDinterface). For testing purposes it is convenient to open a second telnet connection, e.g. with a terminal program such as Putty.
+===== Targets =====
+The PS includes two targets, //zynq.cpu0// and //zynq.cpu1//. These can be listed with the  command ''targets''.
+<code>
+    TargetName         Type       Endian TapName            State
+--  ------------------ ---------- ------ ------------------ ------------
+* zynq.cpu0          cortex_a   little zynq.dap           running
+  zynq.cpu1          cortex_a   little zynq.dap           running
+</code>
+The star denotes the current target, e.g. the ''reg'' command will list all registers. To list the registers of cpu1 you have to change the current target with ''targets zynq.cpu1''.
+When halting the running targets with ''halt'', the state of the two targets are listed in the console, e.g.
+<code>
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x60000113 pc: 0x00101834
+MMU: disabled, D-Cache: disabled, I-Cache: disabled
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x60000193 pc: 0xffffff34
+MMU: disabled, D-Cache: disabled, I-Cache: disabled
+</code>
+The output shows the state of the two targets. <WRAP center round important 60%>
+The first three lines always show the state of the current target, the next three lines the other target. If cpu1 is current, its state will be listed first followed by the state of cpu0.
+</WRAP>
+===== Problems =====
+Bad USB cable connections can lead to errors such as
+<code>
+Info : accepting 'telnet' connection on tcp/4444
+Info : JTAG tap: zynq_pl.bs tap/device found: 0x13722093 (mfg: 0x049 (Xilinx), part: 0x3722, ver: 0x1)
+Info : JTAG tap: zynq.dap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4)
+Warn : zynq.cpu0: ran after reset and before halt ...
+Warn : zynq.cpu1: ran after reset and before halt ...
+Error: DSCR_DTR_RX_FULL, dscr 0x4b086003
+</code>
+In such a case, try another cable.

deep

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