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first_example [2020/09/11 17:10] – [Running Demo Programs] ursgraf | first_example [2020/12/01 14:24] – [Running Demo Programs] ursgraf | ||
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====== First Example ====== | ====== First Example ====== | ||
===== Hello World with System.out ===== | ===== Hello World with System.out ===== | ||
- | * [[first_example_mpc555|Using System.out | + | * [[first_example_mpc555| |
- | * [[first_example_mpc5200|Using System.out | + | * [[first_example_mpc5200| |
- | * [[first_example_microzed|Using System.out | + | * [[first_example_microzed| |
- | * [[first_example_zybo|Using System.out | + | * [[first_example_zybo| |
+ | ===== Developing on the Avnet MicroZed Board ===== | ||
+ | As this board contains a FPGA which must be loaded with a suitable configuration, | ||
+ | * [[first_example_microzed_sysdev| System Developer]] | ||
+ | * [[first_example_microzed_appdev| Application Developer]] | ||
+ | * [[first_example_microzed_deploy| Deploying]] | ||
===== Running Demo Programs ===== | ===== Running Demo Programs ===== | ||
The deep runtime library offers a couple of demo programs, e.g. using serial output or flashing a led. Create a new project as given above and open the //deep// project file. Navigate to // | The deep runtime library offers a couple of demo programs, e.g. using serial output or flashing a led. Create a new project as given above and open the //deep// project file. Navigate to // | ||
- | {{: | + | {{: |
Edit the // | Edit the // | ||
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# enter names of rootclasses, | # enter names of rootclasses, | ||
# | # | ||
- | rootclasses = "ch.ntb.inf.runtime.zynq7000.microzed.demo.Blinker"; | + | rootclasses = "org.deepjava.runtime.zynq7000.microzed.demo.Blinker"; |
</ | </ | ||
- | Create a run configuration and run the program as given in [[first_example|First Example]] | + | Create a run configuration and run the program as given in [[first_example|Hello World with System.out]]. Be aware of the fact that all the examples using //flink// devices (which are implemented in the FPGA) need a suitable configuration loaded into the FPGA at startup. |