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runtime_library:drivers:start [2023/03/23 09:41] – [Zynq7000] ursgraf | runtime_library:drivers:start [2023/03/23 09:42] – [Zynq7000] ursgraf | ||
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===== Zynq7000 ===== | ===== Zynq7000 ===== | ||
+ | When using | ||
==== flink Devices ==== | ==== flink Devices ==== | ||
The Zynq7000 incorporates a configurable programmable logic (PL) block, which is an FPGA. We support the configuration of the PL with [[https:// | The Zynq7000 incorporates a configurable programmable logic (PL) block, which is an FPGA. We support the configuration of the PL with [[https:// |