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dev:zynq7000pl
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PL Configuration on the Zynq7000
- Use Xilinx Vivado to create a new configuration for the programmable logic part of the Zynq7000 (PL) according to https://flink-project.ch/flink_vhdl#building. Result is a bit-file, e.g. flink2.bit.
- Using Vivado, create a new Zynq7000 project following the instructions in 01_mzpz_zynq_intro_2016_4_01.pdf. Export hardware platform to SDK. We use this project solely for that SDK.
- Launch the SDK to create a simple Application, see 02_mzpz_zynq_hello_world_2016_4_01.pdf. This step is not really necessary!
- Launch the SDK to create a FSBL (first stage boot loader), see 04_mzpz_fsbl_boot_2016_4_01.pdf.
dev/zynq7000pl.1640849624.txt.gz · Last modified: 2021/12/30 08:33 by ursgraf
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