Use Xilinx Vivado to create a new configuration for the programmable logic part of the Zynq7000 (PL) according to https://flink-project.ch/flink_vhdl#building. Result is a bit-file, e.g. flink2.bit.
dev/zynq7000pl.1640849031.txt.gz · Last modified: 2021/12/30 08:23 by ursgraf