deep

a Cross Development Platform for Java

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dev:start [2017/03/20 09:58] – sfinkdev:start [2019/02/25 16:40] – [Crosscompiler] ursgraf
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   * [[.:file_formats]|File Formats]]   * [[.:file_formats]|File Formats]]
   * [[.:HString|HStrings (String-Handling in the Compiler)]]   * [[.:HString|HStrings (String-Handling in the Compiler)]]
 +  * [[openocd:start|OpenOCD]]
 </box> </box>
 </WRAP> </WRAP>
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 ===== Crosscompiler ===== ===== Crosscompiler =====
-Our **deep** compiler translates Bytecode into machine code for a certain processor. To optimize for speed and code size and to make use of register based architecture - such as PPC - we transform the Bytecode in a first step into [[.:CrossCompiler:SSA|Static Single Assignment Form, SSA]]. This form is simple and platform independent and can be used for various optimizations. In a second step, which is platform specific, registers are allocated and code is generated. +Our **deep** compiler translates Bytecode into machine code for a certain processor. To optimize for speed and code size and to make use of register based architecture - such as PPC or ARM - we transform the Bytecode in a first step into [[.:CrossCompiler:SSA|Static Single Assignment Form, SSA]]. This form is simple and platform independent and can be used for various optimizations. In a second step, which is platform specific, registers are allocated and code is generated. 
  
 ==== Frontend ==== ==== Frontend ====
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 ==== Backend ==== ==== Backend ====
 For each supported architecture a specific backend is necessary. As a first step, registers are assigned for all SSA instruction results. After this machine instructions can be issued for the target. Finally the linker combines everything into a executable target image.\\ For each supported architecture a specific backend is necessary. As a first step, registers are assigned for all SSA instruction results. After this machine instructions can be issued for the target. Finally the linker combines everything into a executable target image.\\
-Currently, PowerPC code can be generated. As target processors we use mpc555 and mpc5200. +Currently, PowerPC and ARMv7 code can be generated. As target processors we use mpc555 and mpc5200 for PowerPC and the Zynq-7000 with a dual core ARM Cortex-A9 processor as an ARM target. 
  
 ===== Further Components ===== ===== Further Components =====
dev/start.txt · Last modified: 2022/12/20 11:30 by ursgraf

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