dev:start
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| Both sides previous revisionPrevious revisionNext revision | Previous revisionNext revisionBoth sides next revision | ||
| dev:start [2017/03/20 09:58] – sfink | dev:start [2018/10/10 11:02] – ursgraf | ||
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| * [[.: | * [[.: | ||
| * [[.: | * [[.: | ||
| + | * [[openocd: | ||
| </ | </ | ||
| </ | </ | ||
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| ==== Backend ==== | ==== Backend ==== | ||
| For each supported architecture a specific backend is necessary. As a first step, registers are assigned for all SSA instruction results. After this machine instructions can be issued for the target. Finally the linker combines everything into a executable target image.\\ | For each supported architecture a specific backend is necessary. As a first step, registers are assigned for all SSA instruction results. After this machine instructions can be issued for the target. Finally the linker combines everything into a executable target image.\\ | ||
| - | Currently, PowerPC code can be generated. As target processors we use mpc555 and mpc5200. | + | Currently, PowerPC |
| ===== Further Components ===== | ===== Further Components ===== | ||
dev/start.txt · Last modified: 2022/12/20 11:30 by ursgraf
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