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dev:crosscompiler:backend_arm:register_allocation [2018/11/13 16:20] – [Register Usage] ursgraf | dev:crosscompiler:backend_arm:register_allocation [2019/08/29 16:02] – [Parameter Passing] ursgraf | ||
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===== Register Usage ===== | ===== Register Usage ===== | ||
- | Registers can be classified as // | ||
| Register | State | Use | | | Register | State | Use | | ||
- | | R0 | volatile | 1st. parameter, return value | | + | | R0 | volatile | 1st. parameter, local variables, return value | |
- | | R1 | volatile | 2nd. parameter, return value (if long, lower 4 bytes of long) | | + | | R1 | volatile | 2nd. parameter, local variables, return value (if long, lower 4 bytes of long) | |
| R2-R5 | volatile | further parameters, local variables | | | R2-R5 | volatile | further parameters, local variables | | ||
| R6 | dedicated | scratch register | | | R6 | dedicated | scratch register | | ||
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| R14 | dedicated | link register, scratch register | | | R14 | dedicated | link register, scratch register | | ||
| R15 | dedicated | PC | | | R15 | dedicated | PC | | ||
- | | D0 | volatile | + | | D0 | dedicated| scratch register | |
- | | D1-D6 | volatile | further | + | | D1 | dedicated| scratch register, return value | |
+ | | D2-D6 | volatile | parameters, local variables | ||
| D7-D10 | volatile | local variables | | | D7-D10 | volatile | local variables | | ||
| D11-D31 | nonvolatile | local variables | | | D11-D31 | nonvolatile | local variables | | ||
+ | | S0,S1 | dedicated| scratch register | | ||
+ | | S2 | volatile | 1. parameter, local variables, return value | | ||
+ | | S3-S13 | volatile | further parameters, local variables | | ||
+ | | S14-S21 | volatile | local variables | | ||
+ | | S22-S31 | nonvolatile | local variables | | ||
+ | |||
Beside the 32 extension register of the VFPv3 with double prescision, there are 32 single prescision register which are interleaved with the first 16 double prescision registers. When the register allocator reserves a double precision register, e.g. d3, it will mark s6 and s7 as reserved as well. When a single precision register is reserved, e.g. s28, it will mark d14 as reserved as well. | Beside the 32 extension register of the VFPv3 with double prescision, there are 32 single prescision register which are interleaved with the first 16 double prescision registers. When the register allocator reserves a double precision register, e.g. d3, it will mark s6 and s7 as reserved as well. When a single precision register is reserved, e.g. s28, it will mark d14 as reserved as well. | ||
Local variables are assigned volatile registers. However, if the live range of an SSA value incorporates a method call, a nonvolatile register has to be used. These will be assigned in decreasing order from R12/D31. As working registers volatile registers are used. If there are not enough of them, nonvolatiles (just below the locals) are assigned. \\ | Local variables are assigned volatile registers. However, if the live range of an SSA value incorporates a method call, a nonvolatile register has to be used. These will be assigned in decreasing order from R12/D31. As working registers volatile registers are used. If there are not enough of them, nonvolatiles (just below the locals) are assigned. \\ | ||
- | Care must be taken when defining which register | + | Care must be taken when defining which extension registers |
Optimization: | Optimization: | ||
- | For the translation of certain SSA instructions (e.g. of type long) further auxiliary registers are needed. They are assigned and reserved by the register allocator as well. If FPR's are needed for auxiliary registers, they are not reserved but F20..F22 will be used TODO. They are exclusively used in compiler specific subroutines and never need saving. | + | For the translation of certain SSA instructions (e.g. of type long) further auxiliary registers are needed. They are assigned and reserved by the register allocator as well. |
- | ==== Parameter Passing ==== | + | ===== Parameter Passing |
- | Parameters are passes | + | Parameters are passed |
- | In the interface //armPPC/ | + | In the interface //arm/ |
+ | |S0|S1|S2|S3|S4|S5|S6|S7|S8|S9|S10|S11| | ||
+ | | D0 || D1 || D2 || D3 || D4 || D5 || | ||
+ | | ^| ^^a| ^ b ^^c| ^ d ^^ | ||
- | ==== Locals on the Stack ==== | + | ===== Locals on the Stack ===== |
Most SSA instruction have 2 operands and a result. Each of them can reside on the stack. Operands must be fetched into a free register, the result must be stored onto the stack. A single SSA instruction '' | Most SSA instruction have 2 operands and a result. Each of them can reside on the stack. Operands must be fetched into a free register, the result must be stored onto the stack. A single SSA instruction '' | ||
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| R4 | dedicated | long part of first operand of SSA instruction | | | R4 | dedicated | long part of first operand of SSA instruction | | ||
| R3 | dedicated | long part of second operand of SSA instruction | | | R3 | dedicated | long part of second operand of SSA instruction | | ||
+ | | D11 | dedicated | result register or third operand of '' | ||
+ | | D12 | dedicated | first operand of SSA instruction | | ||
+ | | D13 | dedicated | second operand of SSA instruction | | ||
+ | | S22 | dedicated | result register or third operand of '' | ||
+ | | S23 | dedicated | first operand of SSA instruction | | ||
+ | | S24 | dedicated | second operand of SSA instruction | | ||
+ | When dividing numbers of type long, a large number of auxiliary registers are necessary. For these cases the register allocation is run with a reduced register set with the same reserved registers as above given above. |